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EURETILE : European Reference Tiled Architecture Experiment

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Created on Tuesday, 23 March 2010 Written by Lutz Schubert

Project Description

EURETILE investigates and implements brain-inspired foundational innovations to the system architecture of massively parallel tiled computer architectures and the corresponding programming paradigm. The execution target is a many-tile HW platform, equipped with a many-tile simulator. A set of SW process - HW tile mapping candidates are generated by the holistic SW tool-chain using a combination of analytic and bio-inspired methods.
The Hardware dependent Software is then generated, providing OS services with maximum efficiency/minimal overhead. The many-tile simulator collects profiling data, closing the loop of the SW tool chain. Fine-grain parallelism inside processes is exploited by optimized intra-tile compilation techniques. The elementary HW tile is a multi-processor, which includes a Distributed Network Processor (for inter-tile communication), a floating-point VLIW processor (for numerical intensive computations), and a RISC processor (for control, user interface and sequential computations). Furthermore, EURETILE investigates and implements the innovations for equipping the existing full-European elementary HW tile with high-bandwidth, low-latency brain-like inter-tile communication (emulating 3 levels of connection hierarchy, namely neural columns, cortical areas and cortex). The innovations will secure a 15+ year HW road-map of low-power and fault-tolerant excellence.
EURETILE leverages on the working SW and HW prototypes of the innovative multi-tile HW paradigm and SW tool-chain developed by the FET-ACA SHAPES Integrated Project (2006-2009). This background knowledge includes working tile silicon and board, a multi-tile simulator (running up to eight tiles), and a complete SW tool-chain including a parallel programming and an automatic mapping/optimization environment (Distributed Operation Layer), a specialized OS (DNA-OS automatically generated for both RISC and VLIW) integrated with Linux RT, and an optimizing compiler co-designed with the HW tile.

Like S(o)OS, EURETILE is investigating into the distribution of applications into a more or less dynamic environment.

Project Overview

Project Title: EureTile: European Reference Tiled Architecture Experiment
Project Start Date: 01.01.2010
Contact: Pier Stanislao Paolucci, INFI
Consortium: INFI - Istituto Nazionale di Fisica Nucleare, IT
ETH - Eidgenössische Technische Hochschule Zürich, CH
RWTH - Rheinisch-Westfälische Technische Hochschule Aachen, DE
TARGET - The ASIP Company, BE
TIMA - Université Joseph Fourier, FR
Website: http://euretile.roma1.infn.it

Collaboration with S(o)OS

  • discussion on potential collaboration was initiated with ETH on the topic of application distribution
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