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		<title>Related News</title>
		<description><![CDATA[S(o)OS - Service-oriented Operating Systems]]></description>
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			<title>Polca - Programming Large Scale Heterogeneous Infrastructures</title>
			<link>http://www.soos-project.eu/index.php/related-news/145-polca-programming-large-scale-heterogeneous-infrastructures</link>
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			<description><![CDATA[<div class="feed-description"><p>Polca (Programming Large Scale Heterogeneous Infrastructures) is a project proposal, pending of aproval, submitted to call 10 of ICT-2013-3.4, “Advanced&nbsp;Computing, embedded and Control Systems” as an approach to bring together High Performance&nbsp;and Embedded Computing.&nbsp;</p>
</div>]]></description>
			<author>rubio@hlrs.de (Daniel Rubio Bonilla)</author>
			<category>Related News</category>
			<pubDate>Tue, 11 Jun 2013 11:19:50 +0000</pubDate>
		</item>
		<item>
			<title>MyThos - Operating System for Many Threads</title>
			<link>http://www.soos-project.eu/index.php/related-news/141-mythos-many-thread-opearting-system</link>
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			<description><![CDATA[<div class="feed-description"><p>MyThos (modular Operating System for Massively Threaded applications) is a BMBF (German Ministry of Education and Research) funded project included in the call for initiatives to further increase scale and performance of industrially relevant applications for the purpose of full commercial exploitation of HPC systems.</p>
</div>]]></description>
			<author>rubio@hlrs.de (Daniel Rubio Bonilla)</author>
			<category>Related News</category>
			<pubDate>Tue, 21 May 2013 10:37:00 +0000</pubDate>
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		<item>
			<title>The JUNIPER EU project is started</title>
			<link>http://www.soos-project.eu/index.php/related-news/139-juniper</link>
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			<description><![CDATA[<div class="feed-description"><p><a href="http://www.juniper-project.org/">JUNIPER</a> (Java Platform for High Performance and Large Scale Real-Time Data) is a STREP project of the FP7 programme of the EU. The aim of the project is to conduct research on innovative technology for supporting Real-Time Big Data applications.</p>
</div>]]></description>
			<author>g.lipari@sssup.it (Giuseppe Lipari)</author>
			<category>Related News</category>
			<pubDate>Mon, 27 May 2013 13:32:07 +0000</pubDate>
		</item>
		<item>
			<title>LLVM 3.3 new features</title>
			<link>http://www.soos-project.eu/index.php/related-news/138-llvm-3-3-new-features</link>
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			<description><![CDATA[<div class="feed-description"><p>Next week will be released the version 3.3 of LLVM and CLANG infrastructure and it includes new exciting features.</p>
</div>]]></description>
			<author>rubio@hlrs.de (Daniel Rubio Bonilla)</author>
			<category>Related News</category>
			<pubDate>Mon, 27 May 2013 06:38:32 +0000</pubDate>
		</item>
		<item>
			<title>Next generations consoles to use hybrid architectures with unified memory space.</title>
			<link>http://www.soos-project.eu/index.php/related-news/137-next-generations-consoles-to-use-hybrid-architectures-with-unified-memory-space</link>
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			<description><![CDATA[<div class="feed-description"><p><span style="line-height: 1.3em;">The next generation of high performing gaming consoles, the PlayStation 4 and Xbox One, will both use a hybrid architecture using a semi-custom SoC design based on AMD's modules.</span></p>
</div>]]></description>
			<author>rubio@hlrs.de (Daniel Rubio Bonilla)</author>
			<category>Related News</category>
			<pubDate>Mon, 27 May 2013 05:35:49 +0000</pubDate>
		</item>
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			<title>AMD, Intel and Nvidia present new accelerators in SC12</title>
			<link>http://www.soos-project.eu/index.php/related-news/134-amd-intel-and-nvidia-present-new-accelerators-in-sc12</link>
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			<description><![CDATA[<div class="feed-description"><p>Advanced Micro Devices (AMD), Intel and Nvidia have presented their new compute accelerators cards for high-performance computing (HPC) at the SuperComputing Conference &amp; Exhibition (SC12), taking place in Salt Lake City (USA).</p>
<p>The new products deliver better theoretical performance compared to previous generation without increasing the energy consumption. To achieve this the level of parallelism (internal computing cores) is greatly increased.</p>
</div>]]></description>
			<author>rubio@hlrs.de (Daniel Rubio Bonilla)</author>
			<category>Related News</category>
			<pubDate>Wed, 14 Nov 2012 14:38:15 +0000</pubDate>
		</item>
		<item>
			<title>Adapteva 4096-Core Processor</title>
			<link>http://www.soos-project.eu/index.php/related-news/130-adapteva-4096-core-processor</link>
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			<description><![CDATA[<div class="feed-description"><p>
<p>Adapteva has announced that is developing a new multicore architecture with up to 4,096 RISC processing cores on a single die.</p>
<p>The company claims that the chip will be achieving a performance efficiency of 70 GFlops per watt. The flagship processor would produce more than five TFlops in double precision at 700 Mhz.</p>
</div>]]></description>
			<author>rubio@hlrs.de (Daniel Rubio Bonilla)</author>
			<category>Related News</category>
			<pubDate>Thu, 22 Mar 2012 08:19:23 +0000</pubDate>
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		<item>
			<title>Programming features for a parallel world</title>
			<link>http://www.soos-project.eu/index.php/related-news/126-programming-features-for-a-parallel-world</link>
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			<description><![CDATA[<div class="feed-description"><p>Programming models have evolved over decades to for single-core, single-processor machines. Support for distributed and even parallel execution of code is not an intrinsic feature to most current programming languages and instead have to be painstakingly added and handled by the developer.</p>
<p>Intel published a set of features that new programming models will need to address - find the full article on <a href="http://www.hpcwire.com/hpcwire/2012-02-23/retrofitting_programming_languages_for_a_parallel_world.html" target="_blank" title="Programming Languages for a Parallel World">HPCWire</a>.</p></div>]]></description>
			<author>schubert@hlrs.de (The S(o)OS Consortium)</author>
			<category>Related News</category>
			<pubDate>Thu, 01 Mar 2012 22:00:00 +0000</pubDate>
		</item>
		<item>
			<title>Details on IBM's Blue Gene Q available</title>
			<link>http://www.soos-project.eu/index.php/related-news/124-details-on-ibms-blue-gene-q-available</link>
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			<description><![CDATA[<div class="feed-description"><p>More and more information about the latest Blue Gene/Q(TM) (BGQ) series of supercomputers by IBM is becoming available. Capitalizing on the experience gained by building the two earlier generations of supercomputers (the Blue Gene/L(TM) and Blue Gene/P(TM) series), in the BlueGene/Q series IBM has put together a number of innovations that promise to realize unprecedented performance, scalability, reliability and at the same time energy efficiency.</p>
</div>]]></description>
			<author>cucinotta@sssup.it (Tommaso Cucinotta)</author>
			<category>Related News</category>
			<pubDate>Fri, 02 Mar 2012 11:58:49 +0000</pubDate>
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