Explore, develop, and validate new mechanisms to fully exploit the power of multi-core architectures. In particular, HPC and embedded experimentation platforms are being built incrementally to be used by the ParMA consortium.

The main tasks include

• Optimisation of exchanges between socket's cores
• Monitoring the frequency of the timer interrupt to improve the efficiency of cache use
• Optimisation of hyper-threading
• Specification and implementation of checkpointing/restarting facilities
• Optimisation of I/O performance
• Optimisation of numerical libraries by developing multi-threaded versions thereof