ParMA is a three-year project (ITEA2 ~ 06015) that has started in June 2007 and will last till May 2010.

Goals

• Develop advanced technologies to exploit fully the power of multi-core architectures
• Deliver substantial performance improvements for conventional HPC (High Performance Computing) and for mainstream applications
• Enable the advent of power-intensive innovative embedded applications

For further information please visit our Achievements - Section.

Challenges

• Since most existing HPC applications are designed as a set of independent processes communicating and synchronising through efficient Message Passing (MPI) methods with each process being bound to a processor, programming paradigms and tools must be developed to help restructure applications so they fully benefit from multilevel parallelism offered by new multicore architectures.
• Due to the huge number of threads that multicore processors will be able to run in parallel, dramatic improvements must be achieved in the way threads are allocated and monitored to minimise memory access - i.e. data exchanges between threads.
• More powerful parallel programming, debugging and performance analysis tools are needed, scalable and more user-friendly than today.
• Since parallel architectures are coming in different forms - SMP, NUMA, MPSoC, etc. - parallel debugger and performance tools must be able to run in these various contexts as well.
• Because embedded systems will also be built with multicore processors, multi-level parallel design, programming and execution models must be defined and tools developed to design efficient interconnecting networks for MPSoC.
• Because each domain - simulation, virtual reality, avionics, etc. - has its own characteristics and specific constraints, it is necessary to experiment with applications from these different domains to validate the proposed approach and to identify better the commonalities and the specifics.